- 20+ design wins awarded by leading semiconductor and system companies
- Multiple first-pass silicon successes achieved with Cadence IP
- IP silicon tested and characterized to ensure robust system interoperability
- Early N3 and N4 customer engagements underway
SAN JOSE, Calif.–(BUSINESS WIRE)–Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced a wide range of leading semiconductor and system customers have successfully adopted the comprehensive line-up of Cadence® Design IP in TSMC’s industry-leading 5nm process technology. Designed to the latest state-of-the-art interface standards, the Cadence’s Design IP portfolio enables customers to develop the most advanced SoCs for the most demanding applications, including high-performance computing (HPC), artificial intelligence/machine learning (AI/ML), networking, storage, and automotive. The IP portfolio from Cadence in TSMC’s N5 process includes 112/56/25/10 Gbps Ethernet PHY/MAC, PCIe 6.0/5.0/4.0/3.1 PHY/Controller, 40Gbps Ultralink™ D2D PHY, and complete PHY/Controller for GDDR6, DDR5/4, and LPDDR5/4x.
Cadence’s design IP in TSMC’s N5 process delivers optimal power, performance and area (PPA) with rich feature sets to enable uncompromised differentiation, versatility and innovation for large-scale SoC designs. In addition, Cadence provides full subsystem deliveries with integrated PHY and controller IP to simplify integration, minimize risks, and enable faster time to market.
“TSMC worked closely with Cadence, our long-standing ecosystem partner, to enable leading-edge designs, which deliver significant power, performance and area improvements on our advanced technologies,” said Suk Lee, vice president of the Design Infrastructure Management Division at TSMC. “The strong collaboration between Cadence’s Design IP and TSMC’s IP9000 teams promotes high-quality IP delivery to help our mutual customers achieve first-pass silicon success and faster time-to-market.
“Cadence has collaborated with TSMC for decades to provide high-quality silicon-proven IP on advanced process nodes to meet the most demanding requirements for HPC, AI/ML, networking, storage, and automotive applications,” said Rishi Chugh, vice president of Design IP Product Management at Cadence. “The wide adoption of our Design IP in TSMC’s N5 process demonstrates the excellence and quality of Cadence’s Design IP, which is empowering customers to design highly differentiated product solutions.”
The N5 Design IP portfolio is part of the broader Cadence IP portfolio that supports the Cadence Intelligent System Design™ strategy. Through the continued development of our comprehensive Design IP portfolio, Cadence is enabling customers to achieve SoC design excellence at advanced nodes. For more information, please visit www.cadence.com/go/designipport.
Cadence is a pivotal leader in electronic systems design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial and healthcare. For eight years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For. Learn more at cadence.com.
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